1. Field of the Invention
This invention relates to dynamic random access memories (DRAMs) and, more particularly, to circuits for testing performance of a self-refreshing DRAM.
2. Prior Art
A self-refreshing DRAM has a longer external access time when an external access is requested and an internal self refresh cycle is in progress. An external access cycle cannot be started until an internal self refresh cycle is completed.
Consequently, a need exists for a technique to measure worst-case external access time for a DRAM.
The present invention provides an access delay test circuit for a self-refreshing DRAM. Self-refreshing DRAMS have External Access Cycles for reading in and writing out external data in specific rows of the DRAM. Self-refreshing DRAMS also include internal refresh cycles that periodically refresh the memory cells in each row of the DRAM. The present invention provides a delay time prior to an external access cycle. Delay times access when an ongoing internal refresh cycle must be completed before an external access cycle can be started. The present invention provides a normal mode of operation and a test mode of operation that always starts an internal refresh cycle prior to initiation of execution of an external access cycle. The invention provides that, during the test mode of operation, the signal, which normally starts an external refresh cycle, is disabled by control logic so that no internal refresh cycles are initiated by a request signal for an internal refresh cycle. In the test mode of operation, upon receipt of an external access request, an address transition detector circuit sends a stable address transition addr_stable signal to the control logic which immediately initiates an internal refresh cycle and delays initiation of an external access cycle. In the test mode, an internal refresh cycle is always started first and is completed prior to initiation of execution of the external access cycle. Consequently, the present invention provides a technique for readily testing performance of a DRAM when an external access cycle is always maximally delayed by initiation of an internal refresh cycle before an external access cycle is initiated.
An arbitration and control system having a test mode that provides an access-delay test circuit for a self-refresh DRAM includes an address transition detection block that receives an address transition signal a_in and that provides an addr_stable output signal to indicate that an address transition has occurred and that a new address is stable. A refresh control block receives an internal refresh request signal ref_req signal, the addr_stable signal, and a row-address-select xras_time1_b signal and that provides a ref_time_b output signal that initiates an internal refresh of a DRAM row. A RAS control block receives the addr_stable signal and the ref_time_b signal and provides a row-address-select xras_time1_b output signal that selects a DRAM row for an external read or write operation.
The refresh control block further includes means for operating the refresh control block in a normal mode and means for operating the refresh control block in a test mode to disable normal generation of internal refresh cycles and to always provide an internal refresh cycle preceding any external row access select signal.
For both the normal mode and the test mode, the arbitration and control system has an address transition detection block that receives an address transition signal a_in and that provides an addr_stable output signal to indicate that an address transition has occurred and that a new address signal is stable.
The arbitration and control system has an internal refresh control block that receives a refresh request signal ref_req signal, the addr_stable signal, and a row-address-select xras_time1_b signal and that in the normal mode of operation provides a ref_time_b output signal that initiates an internal refresh of a DRAM row.
The arbitration and control system has a RAS control block that in both modes of operation receives the addr_stable signal and the ref_time_b signal and that provides a row-address-select xras_time1_b output signal that selects a DRAM row for a read or write operation.
The internal refresh control block includes means for operating the internal refresh control block in a normal mode and means for operating the refresh control block in a test mode to disable normal generation of an internal refresh cycle and to always provide an internal refresh cycle preceding initiation of any external row access cycle.
The means for operating the refresh control block in a test mode disables normal generation of internal refresh cycles. To provide an internal refresh cycle preceding any external row access select cycle, the addr_stable signal going active always triggers a ref_time_b output signal before an xras_time_b output signal to thereby add a worst case delay to initiation of an external row access cycle.
The means for operating the refresh control block in a test mode includes a test terminal for receiving a test_r signal and also includes a first and a second gate. The first gate is closed by an active test_r signal for disabling the output signal of the RAS control box such that no strt_ref_b or set_ref_rq_b signal passes to trigger the ref_time_b output signal. The first gate is opened by an inactive test_r signal enabling the output signal of the RAS control box such that the strt_ref_b or set_ref_rq signal triggers the ref_time_b output signal. The second gate is opened by an active test_r signal to provide a path for an addr_stable signal to trigger a ref_time_b output signal. The second gate is closed by an inactive test_r signal to close the path for an addr_stable signal to trigger an internal refresh ref_time_b output signal.
In the test mode, the leading edge of the addr_stable signal triggers generation of the ref_time_b signal and the trailing edge of the addr_stable signal initiates generation of an xras_time_b signal always after a ref_time_b signal to provide the xras_time_b signal preceded by a ref_time_b signal.
The refresh control block includes an idle control block that provides an output signal when the xras_time1_b signal is inactive and that provides no output signal when the addr_stable signal is active to thereby inhibit the ref_time_b output signal and to prevent initiation of an internal refresh of a DRAM row. A 3-input AND function receives an output signal from the arbitration latch, the output signal from the idle control block, and the xras_time1_b signal such that the output signal of the 3-input AND function triggers a timer circuit that provides the ref_time_b signal.
A refresh timer circuit provides a predetermined active pulse width to the ref_time_b signal to properly time the refresh access duration.
The RAS control block includes a RAS flip-flop circuit that is set by the addr_stable signal and that is reset by the xras_time1_b signal to hold an external RAS cycle request. The RAS flip-flop circuit has an output signal that is gated through a two-input AND gate with an inactive ref_time_b signal.
A RAS timer circuit provides a predetermined active pulse width to the xras_time1_b signal to properly time the duration of an external access to the DRAM memory device.
A method according to the present invention is provided for testing a self-refresh DRAM. The method provides for operating the refresh control block in a normal mode in which internal row refreshing and external row accessing cycles are initiated depending upon their request times. Alternatively operating the refresh control block in a test mode disables normal generation of an internal refresh cycle and always provides that an internal refresh cycle precedes any external row access selection cycle.